ADP1046ACPZ-R7 datasheet(61/96 Pages) AD

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Data Sheet

ADP1046

Rev. 0 | Page 61 of 96

Bits

Bit Name

R/W

Description

[1:0]

OVP sampling

R/W

The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP

threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using

these bits. If the number of samples is increased, the average voltage must be greater than the

OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average

voltage must be greater than the OVP threshold for both cycles.

Bit 1

Bit 0

Additional Sampling (μs)

0 (one sample sets the OVP flag)

80 (two samples set the OVP flag)

160 (three samples set the OVP flag)

240 (four samples set the OVP flag)

Table 52. Register 0x34—VS1 Undervoltage Limit (UVP)

Bits

Bit Name

R/W

Description

End of cycle

shutdown

R/W

This bit is valid only when the OUTAUX pin is used for regulation. When any flag shuts down the

power supply, the OUTAUX PWM is immediately shut down. This bit specifies when the other PWM

outputs are shut down.

1 = all other PWM outputs are shut down at the end of the switching cycle.

0 = all other PWM outputs are immediately shut down.

[6:0]

VS1 UVP setting

R/W

These bits set the UVP limit to one of 128 settings. The UVP limit can be programmed from 0% to

158.75% of the nominal VS1 voltage. Each LSB increases the voltage by 158.75%/128 = 1.25%. In

reality, there are 81 usable settings, which program the UVP threshold from 0% to 100% of the

nominal VS1 voltage. The VS1 UVP threshold is calculated as follows:

VS1_UVP_Threshold = [(VS1_UVP_Setting + 1)/128] × 1.6 V − 12.5 mV

For example, if the VS1 UVP setting is 60, then

VS1_UVP_Threshold = [(60 + 1)/128] × 1.6 V − 12.5 mV = 750 mV

Setting these bits to 0 gives a UVP limit of 0% of the nominal VS1 voltage.

Setting these bits to 72 (0x48) gives a UVP limit of 90% of the nominal VS1 voltage.

Setting these bits to 76 (0x4C) gives a UVP limit of 95% of the nominal VS1 voltage.

Setting these bits to 80 (0x50) gives a UVP limit of 100% of the nominal VS1 voltage.

Setting these bits to 127 (0x7F) gives a UVP limit of 158.75% of the nominal VS1 voltage.

Table 53. Register 0x35—Line Impedance Limit

Bits

Bit Name

R/W

Description

[7:0]

Line impedance

limit

R/W

This value sets the threshold at which the line impedance flag is enabled. This 8-bit value is

compared with the line impedance value (Register 0x1F). If the line impedance value exceeds this

value, the line impedance flag is set (Register 0x02, Bit 2).

Table 54. Register 0x36—Load Line Impedance

Bits

Bit Name

R/W

Description

Load line enable

R/W

Set this bit to enable the load line.

[6:4]

Slew rate

R/W

These bits set the load line slew rate limit, which determines the maximum slew rate for changing

the reference when adjusting the output load line value.

Bit 6

Bit 5

Bit 4

Maximum Slew Rate Duration

200 mV/ms

100 mV/ms

50 mV/ms

25 mV/ms

12.5 mV/ms

6.25 mV/ms

3.125 mV/ms

1.5625 mV/ms (4 LSB/ms)

Reserved

R/W

Reserved.

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