ADP1046ACPZ-R7 datasheet(39/96 Pages) AD

39 / 96 page

Data Sheet

ADP1046

Rev. 0 | Page 39 of 96

GENERAL CALL SUPPORT

The ADP1046 is capable of decoding and acknowledging a

general call address. The general call address is supported for

send, write, and read commands that use Address 0x00 as the

slave address. The I2C slave responds to both its own address

and to the general call address (0x00).

Note that all commands start with a slave address with the R/W

bit cleared (set to 0), followed by the command code. This is

also true when using the general call address to communicate

with the I2C slave device.

10-BIT ADDRESSING

The ADP1046 does not support 10-bit addressing as defined in

the I2C specification.

FAST MODE

Fast mode (400 kB/sec) uses essentially the same mechanics

as the standard mode of operation; the electrical specifications

and timing are most affected. The I2C slave is capable of commu-

nicating with a master device operating in standard mode

(100 kB/sec) or fast mode.

REPEATED START CONDITION

In general, a repeated start condition is the absence of a stop

condition between two transfers. The two transfers can be of

any direction type, for example, a transmit followed by a receive

or a receive followed by a transmit. However, the ADP1046 I2C

communication protocol uses the repeated start condition only

when performing a read access (read byte, read word, and block

read). Other uses of the repeated start condition are not allowed.

ELECTRICAL SPECIFICATIONS

All logic complies with the electrical specifications outlined in

the Philips I2C Bus Specification, Version 2.1, dated January 2000.

FAULT CONDITIONS

The I2C protocol provides a very comprehensive set of fault

conditions that are monitored during communication. These

communication faults are error conditions associated with the

data transfer mechanism of the I2C protocol and are explained

in the following sections.

TIMEOUT CONDITION

A timeout condition occurs if any single SCL clock pulse is held

low for longer than the tTIMEOUT, MIN of 25 ms. Upon detecting the

timeout condition, the I2C slave device has 10 ms to abort the

transfer, release the bus lines, and be ready to accept a new start

condition. The device initiating the timeout is required to hold

the SCL clock line low for a minimum of tTIMEOUT, MAX = 35 ms,

guaranteeing that the slave device is given enough time to reset

its communication protocol.

DATA TRANSMISSION FAULTS

Data transmission faults occur when two communicating

devices violate the I2C communication protocol.

Sending Too Few Bits

Transmission is interrupted by a start or stop condition before

a complete byte (eight bits) has been sent. Not supported; any

transmitted data is ignored.

Reading Too Few Bits

Transmission is interrupted by a start or stop condition before

a complete byte (eight bits) has been read. Not supported; any

received data is ignored.

Host Sends or Reads Too Few Bytes

If a host ends a packet with a stop condition before the required

bytes are sent/received, it is assumed that the host intended to

stop the transfer. Therefore, the I2C slave does not consider this

to be an error and takes no action, except to flush any remain-

ing bytes in the transmit FIFO.

Host Sends Too Many Bytes

If a host sends more bytes than are expected for the corre-

sponding command, the I2C slave considers this a data

transmission fault and responds as follows:



NACKs all unexpected bytes as they are received



Flushes and ignores the received command and data

Host Reads Too Many Bytes

If a host reads more bytes than are expected for the corre-

sponding command, the I2C slave considers this a data

transmission fault and sends all 1s (0xFF) as long as the host

continues to request data.

Device Busy

The I2C slave device is too busy to respond to a request from the

master device. Typically SCL clock stretching is involved until

the device is free to communicate.

DATA CONTENT FAULTS

Data content faults occur when data transmission is successful,

but the I2C slave device cannot process the data that is received

from the master device.

Improperly Set Read Bit in the Address Byte

All I2C commands start with a slave address with the R/W bit

cleared (set to 0), followed by the command code. If a host

starts an I2C transaction with R/W set in the address phase

(equivalent to an I2C read), the I2C slave considers this a data

content fault and responds as follows:



ACKs the address byte



NACKs the command and data bytes



Sends all 1s (0xFF) as long as the host continues to

request data

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