ADP1046ACPZ-R7 datasheet(68/96 Pages) AD

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ADP1046

Data Sheet

Rev. 0 | Page 68 of 96

Table 69. Register 0x45—OUTB Rising Edge Timing (OUTB Pin)

Bits

Bit Name

R/W

Description

[7:0]

R/W

This register contains the eight MSBs of the 12-bit t3 time. This value is always used with the top

four bits of Register 0x46, which contains the four LSBs of the t3 time. Each LSB corresponds to

5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and

t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise

and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.

The absolute maximum pulse width is tPERIOD − 5 ns.

Table 70. Register 0x46—OUTB Rising Edge Setting (OUTB Pin)

Bits

Bit Name

R/W

Description

[7:4]

R/W

These bits contain the four LSBs of the 12-bit t3 time. This value is always used with the eight

bits of Register 0x45, which contains the eight MSBs of the t3 time. Each LSB corresponds to

5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and

t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise

and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.

The absolute maximum pulse width is tPERIOD − 5 ns.

Modulate enable

R/W

1 = PWM modulation acts on the t3 edge.

0 = no PWM modulation of the t3 edge.

t3 sign

R/W

1 = negative sign. Increase of PWM modulation moves t3 right.

0 = positive sign. Increase of PWM modulation moves t3 left.

Reserved

R/W

Reserved.

Volt-second balance

source selection

R/W

If this bit is set to 1, the OUTB rising edge is selected as the start of the integration period for

volt-second balance.

Table 71. Register 0x47—OUTB Falling Edge Timing (OUTB Pin)

Bits

Bit Name

R/W

Description

[7:0]

R/W

This register contains the eight MSBs of the 12-bit t4 time. This value is always used with the top

four bits of Register 0x48, which contains the four LSBs of the t4 time. Each LSB corresponds to

5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and

t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise

and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.

The absolute maximum pulse width is tPERIOD − 5 ns.

Table 72. Register 0x48—OUTB Falling Edge Setting (OUTB Pin)

Bits

Bit Name

R/W

Description

[7:4]

R/W

These bits contain the four LSBs of the 12-bit t4 time. This value is always used with the eight

bits of Register 0x47, which contains the eight MSBs of the t4 time. Each LSB corresponds to

5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and

t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise

and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.

The absolute maximum pulse width is tPERIOD − 5 ns.

Modulate enable

R/W

1 = PWM modulation acts on the t4 edge.

0 = no PWM modulation of the t4 edge.

t4 sign

R/W

1 = negative sign. Increase of PWM modulation moves t4 right.

0 = positive sign. Increase of PWM modulation moves t4 left.

[1:0]

Reserved

R/W

Reserved.

Table 73. Register 0x49—OUTC Rising Edge Timing (OUTC Pin)

Bits

Bit Name

R/W

Description

[7:0]

R/W

This register contains the eight MSBs of the 12-bit t5 time. This value is always used with the top

four bits of Register 0x4A, which contains the four LSBs of the t5 time. Each LSB corresponds to

5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and

t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise

and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.

The absolute maximum pulse width is tPERIOD − 5 ns.

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