PPC34C60 datasheet(12/58 Pages) SMSC

12 / 58 page

SMSC DS – PPC34C60

Page 12

Rev. 06/01/2001

ADVANCED INFORMATION

2 PPC34C60 BLOCK DESCRIPTION

The PPC34C60 can be broken down into eight functional blocks as shown in FIGURE 1.

The PPC34C60 implements and complies with the Daisy Chain Specification (Reference 3) through the Daisy Chain

Protocol block. Under the Daisy Chain protocol, the PPC34C60 operates in either Pass-Through or Selected mode.

Pass-Through mode is the power up default, and is electrically transparent to devices further down the chain. When in

Pass-Through mode, the Data Switch gates the control and status lines of the parallel port to the Pass-Through port.

Selected mode connects the System Interface bus to the parallel port. When in Selected mode, the Data Switch gates the

control and status lines to the PPC34C60's Protocol Translator functional block.

The Protocol Translator block gives the PPC34C60 its capability to communicate with the parallel port in either SPP, EPP,

or ECP mode. The Protocol Translator interprets the Multiport Access Protocol (MAP) packets described in the Daisy Chain

Specification (Reference 3). The MAP packets and command codes are described in the Daisy Chain Command Protocol.

The Protocol Translator also decodes the type of parallel port transfer (ie. Address Write/Data Read_Write Cycle) and

provides the proper control of the data to the Registers and Control block and to the Bus Interface block. The PPC34C60's

internal registers, contained in the Register and Control block, control the operation of the chip's internal DRAM Controller,

DMA Controller, and Watchdog Controller. The Bus Interface block controls data transfers between the Parallel Port and

the peripheral's System Interface Bus. The MUX block routes data and control signals to the System Interface.

FIGURE 1 - INTERNAL BLOCK DIAGRAM

Daisy

Chain

P rotocol

Data

Switch

P rotocol

Translator

SPP

EPP

ECP

A_STB

B_STB

Registers

and

Control

Bus

Interface

DRAM

C ontroller

DM A

C ontroller

WDOG

& Piezo

Counters

MU X

SYSTEM

IN TE R FACE

S P E AKE R

Host

Parallel

Port

Pass-Through

Port

nHSTB

nHALF

nHSEL

nHINIT

nHACK

HBSY

HPE

HSLCT

nHERR

HD[0:7]

nPSTB

nPALF

nPSEL

nPINIT

nPACK

PBSY

PPE

PSLCT

nPERR

HD[0:7]

SLCTD

nRESET

SENSE

TEST

nDACK

DREQ

nRAS

nCAS

nDIR

nPID

IN[0:3]

nST[0:2]

nCS[0:3]

SRST

nSRST

SA[0:7]

MA[8:9]

SD[0:15]

nSRD

nSWR

nIO 16

IRQ

XIN, XOUT

YIN, YOUT,

nWDOGEN, PIEZO

nLBAT

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