PPC34C60 datasheet(41/58 Pages) SMSC

41 / 58 page

SMSC DS – PPC34C60

Page 41

Rev. 06/01/2001

ADVANCED INFORMATION

SPP DATA READ TIMING

PARAMETER

MIN

TYP

MAX

UNITS

nINIT controls the direction of the parallel port when in

SPP mode. When nINIT is asserted the data port is driven

by the PPC34C60 and read by the Host.

This time

represents the time from nINIT asserted to HD[0:7] driven

by the PPC34C60. Note: data is not necessarily valid.

[2 SCLK]

125

[3 SCLK]

As soon as the PPC34C60 places valid data onto the

HD[0:7] port lines, the BSY signal is deasserted by the

PPC34C60 to inform the Host that data is now valid.

This time is determined by the host, the PPC34C60 places

no restriction on this time. This time represents the time it

takes the Host to recognize and latch the valid data on

HD[0:7].

n/a

nSTB pulse width. This time represents the duration that

nSEL must be asserted in order for the PPC34C60 to

recognize an edge.

125

[3 SCLK]

Once the Host has latched the Data on HD[0:7] it asserts

the nSTB signal to inform the PPC34C60 to fetch another

byte of data. If the PPC34C60 has to perform a DRAM or

BUS cycle it may have to assert the BSY signal until it has

completed the cycle and has placed valid data on HD[0:7].

This time represents the time from the assertion of nSTB

to the assertion of BSY when appropriate.

334

[8 SCLK]

375

[9 SCLK]

Once the Host has latched the Data on HD[0:7] it asserts

the nSTB signal to inform the PPC34C60 to fetch another

byte of data.

This time represents the time that the

HD[0:7] data will remain valid from the assertion of nSTB.

[2 SCLK]

125

[3 SCLK]

This time (+t6) represents the time it takes the PPC34C60

to fetch and present the next valid data byte on the HD[0:7]

lines. This time will vary significantly based on the type of

access and the BCLK currently selected. These values

are based on BCLK = 2 SCLK.

250

[6 SCLK]

1,292

[5 SCLK]

[13 BCLK]

nINIT controls the direction of the parallel port when in

SPP mode. nINIT deasserted to HD[0:7] released to high

impedance by the PPC34C60.

[2 SCLK]

125

[3 SCLK]

PPC34C60 数据表(PDF) 41 Page - SMSC Corporation

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PPC34C60 数据表(PDF) 41 Page - SMSC Corporation

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