PPC34C60 datasheet(52/58 Pages) SMSC

52 / 58 page

SMSC DS – PPC34C60

Page 52

Rev. 06/01/2001

ADVANCED INFORMATION

FIGURE 22 - PERIPHERAL BUS WRITE CYCLE TIMING

PARAMETER

MIN

TYP

MAX

UNITS

t1 nCS asserted to nWR asserted. This applies to any

and all of the general purpose output pins that have

been configured to operate as "special function" Chip

Select pins. This feature saves the designer from

having to implement costly address decoders.

[1 BCLK-10]

[1 BCLK]

[1BCLK+10]

t2 nIO16 setup required to the assertion of nWR.

t3 nIO16 hold time required from the assertion of nWR.

t4 nWR asserted pulse width.

158

[2 BCLK-10]

168

[2 BCLK]

178

[2BCLK+10]

t5 Write data valid from the assertion of nCS.

[1 BCLK-10]

[1 BCLK]

[1BCLK+10]

t6 Write data valid hold time from the deassertion of

nWR.

[1 BCLK-10]

[1 BCLK]

[1BCLK+10]

t7 nWR deasserted to nCS deasserted.

[1 BCLK-10]

[1 BCLK]

[1BCLK+10]

T8 nWR deasserted to the address incremented (this is

valid only if the AUTOINC bit is set).

[1 BCLK-10]

[1 BCLK]

[1BCLK+10]

valid

Data Valid

Address Valid

Address +1

AUTOINC bit set

nCAS

nRAS

nCS

nIO16

nRD

nWR

SD[0:15]

SA[0:7]

BUSCLK

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