PPC34C60 datasheet(39/58 Pages) SMSC

39 / 58 page

SMSC DS – PPC34C60

Page 39

Rev. 06/01/2001

ADVANCED INFORMATION

FIGURE 12 - SPP DATA WRITE TIMING (PARALLEL PORT SIGNALS

)

This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode.

SPP DATA WRITE TIMING (PARALLEL PORT SIGNALS)

PARAMETER

MIN

TYP

MAX

UNITS

nINIT controls the direction of the parallel

port when in SPP mode. nINIT deasserted

to HD[0:7] released to high impedance by

the PPC34C60.

[2 SCLK]

125

[3 SCLK]

Valid data on HD[0:7] to nSTB asserted

edge.

125

[3 SCLK]

BSY deasserted (low) to nSTB asserted

edge.

nSTB asserted pulse width.

125

[3 SCLK]

Valid data hold from nSTB deasserted

edge.

125

[3 SCLK]

nSTB asserted edge to BSY asserted

edge.

333

[8 SCLK]

375

[9 SCLK]

BSY asserted pulse width. These values

are based on BCLK = 2 SCLK.

1,084

[13 BCLK]

HD[0:7]

nSTB H

nALF H

nSEL H

nINIT H

BSY P

nACK P

PE P

SLCT P

nERR P

PPC34C60 数据表(PDF) 39 Page - SMSC Corporation

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