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PPC34C60 数据表(PDF) 42 Page - SMSC Corporation

部件名 PPC34C60
功能描述  PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
PDF  58 Pages
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制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

PPC34C60 数据表(HTML) 42 Page - SMSC Corporation

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SMSC DS – PPC34C60
Page 42
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 14 - SPP NIBBLE READ (PARALLEL PORT SIGNALS)
This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode. This timing
sequence deviates from that specified in the P1284 specification. It is implemented in a way that requires less host
software overhead and therefore affords higher bandwidth.
The timing shown is for a nibble read of a 16 bit wide resource (DRAM or peripheral BUS). See SPP Nibble Read Timing
parameters.
t2
t4
t5
t6
t4
t5
t6
t4
t5
t6
t4
t1
t7
t8
t3
t3
t3
t3
BIT D3
BIT D7
BIT D2
BIT D6
BIT D1
BIT D5
BIT D0
BIT D4
BIT D8
BIT D9
BIT D10
BIT D11
BIT D12
BIT D13
BIT D14
BIT D15
nSTB H
nALF H
nSEL H
nINIT H
BSY P
nACK P
PE P
SCLT P
nERR P



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