PPC34C60 datasheet(17/58 Pages) SMSC

17 / 58 page

SMSC DS – PPC34C60

Page 17

Rev. 06/01/2001

ADVANCED INFORMATION

An address write cycle is used to select the PPC34C60's address mode for subsequent data write cycles. Table 2 shows

ten types of Address Modes into which the PPC34C60 may be placed. The address write data byte required for each

mode is encoded as '1WBMA3A2A1A0'.

Table 2 also illustrates three separate System Data Bus addressing modes along with DRAM and Internal Registers

addressing.

When the Host Address Write data is 1X100XXX, the PPC34C60 provides unrestricted System Data Bus access for all

subsequent Host Parallel Port data exchanges.

Unrestricted System Data Bus access can also occur following Address Write operations where 1WBMA3A2A1A0 =

1X00(A3-A0), except that in this short hand addressing mode A3-A0 is also written to the least significant four bits of the

PPC34C60 internal Address Register. Address Write operations where 1WBMA3A2A1A0 = 1X01(A3-A0) provides block

count limited System Data Bus access with shorthand addressing.

For example, an Address Write operation in which B = 1, M = 0, and A3A2A1A0 = 0000 selects System Data Bus access

but does not alter the value of the PPC34C60 Address Bus, SA[0:7].

Table 2 - Address Mode Operations

1WBM

A3A2A1A0

ACCESS TYPE

W=1(WRITE)

W=0(READ)

1X00

(A3-A0)

SYSTEM DATA

BUS

Unrestricted Bus Write

(Shorthand Mode)

Unrestricted Bus Read

(Shorthand Mode)

1X01

(A3-A0)

Block Restricted Bus

Write (Shorthand Mode)

Block Restricted Bus

Read (Shorthand Mode)

1X10

0XXX (BUS)

Unrestricted Bus Write

Access

Unrestricted Bus Read

Access

1X10

1XXX

(DRAM)

DRAM

DRAM Write Access

DRAM Read Access

1X11

RRRR

INTERNAL

REGISTERS

Write Internal Register

RRRR

Read Internal Register

RRRR

W = Write

B = Bus

M = Max Count

A3A2A1A0 = Address Selector

RRRR = Register Selector

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