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PPC34C60 数据表(PDF) 43 Page - SMSC Corporation |
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PPC34C60 数据表(HTML) 43 Page - SMSC Corporation |
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43 / 58 page ![]() SMSC DS – PPC34C60 Page 43 Rev. 06/01/2001 ADVANCED INFORMATION SPP NIBBLE READ (PARALLEL PORT SIGNALS) PARAMETER MIN TYP MAX UNITS t1 The PPC34C60 assembles a nibble of data and places it on the status lines. The PPC34C60 then deasserts the BSY signal to inform the Host that a valid nibble is available. 42 [SCLK] ns t2 Once the Host senses that the BSY line is deasserted it will then internally latch the nibble and then assert nSTB to tell the PPC34C60 to get the next nibble. 0 ns t3 It will take the PPC34C60 this amount of time to fetch and present the next nibble of data. 250 [6 SCLK] ns t4 nSTB asserted pulse width 125 [3 SCLK] ns t5 nSTB deasserted pulse width 125 [3 SCLK] ns t6 Once the PPC34C60 has placed the next nibble, this is the time for the Host to latch the nibble and then assert nSTB to tell the PPC34C60 to get the next nibble. 42 [SCLK] ns t7 Once the Host has latched the last nibble it asserts the nSTB signal to inform the PPC34C60 to fetch another more data. If the PPC34C60 has to perform a DRAM or BUS cycle it may have to assert the BSY signal until it has completed the cycle and has placed a valid nibble on the status lines. This time represents the time from the assertion of nSTB to the assertion of BSY when appropriate. 334 [8 SCLK] 375 [9 SCLK] ns t8 This time represents the time it takes the PPC34C60 to fetch and present the next valid nibble on the status lines. This time will vary significantly based on the type of access and the BCLK currently selected. These values are based on BCLK = 2 SCLK. 0 1,084 [13 BCLK] ns |
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