PPC34C60 datasheet(14/58 Pages) SMSC

14 / 58 page

SMSC DS – PPC34C60

Page 14

Rev. 06/01/2001

ADVANCED INFORMATION

3.1 Peripheral System Design

The PPC34C60 simplifies the design of a peripheral to exploit the benefits of IEEE STD 1284, Standard Signaling for a Bi-

Directional Parallel Port (Reference 1). FIGURE 2 depicts a high-level System Block Diagram which shows the peripheral

chip's three primary data paths.

Note that the Parallel Port Data Bus is not switched through the PPC34C60; this allows all daisy chained devices to receive

a special "out of band" Control Packet as defined in the Distec Daisy Chain Specification (Reference 3).

FIGURE 2 - SYSTEM BLOCK DIAGRAM

nPSTB

nPALF

nPSEL

nPINIT

nPACK

PBSY

PPE

PSLCT

nPERR

nHSTB

nHALF

nHSEL

nHINIT

nHACK

HBSY

HPE

HSLCT

nHERR

Host

Parallel Port

Connector

Pass-Through

Parallel Port

Connector

Parallel Port Data Bus

PPC34C60

System

Interface

ISA Peripheral

PPC34C60 数据表(PDF) 14 Page - SMSC Corporation

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