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PPC34C60 数据表(PDF) 56 Page - SMSC Corporation

部件名 PPC34C60
功能描述  PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
PDF  58 Pages
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制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

PPC34C60 数据表(HTML) 56 Page - SMSC Corporation

Back Button PPC34C60 Datasheet HTML 50Page - SMSC Corporation PPC34C60 Datasheet HTML 51Page - SMSC Corporation PPC34C60 Datasheet HTML 52Page - SMSC Corporation PPC34C60 Datasheet HTML 53Page - SMSC Corporation PPC34C60 Datasheet HTML 54Page - SMSC Corporation PPC34C60 Datasheet HTML 55Page - SMSC Corporation PPC34C60 Datasheet HTML 56Page - SMSC Corporation PPC34C60 Datasheet HTML 57Page - SMSC Corporation PPC34C60 Datasheet HTML 58Page - SMSC Corporation  
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SMSC DS – PPC34C60
Page 56
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 26 - DMA TRANSFER CYCLE TIMING
[8-bit peripheral system bus to 4-bit DRAM], (D16=0, RAMSZ[1:0]=[0,0])
[16-bit peripheral system bus to 8-bit DRAM], (D16=1, RAMSZ[1:0]=[0,1])
FIGURE 27 - DMA TRANSFER CYCLE TIMING
[8-bit peripheral system bus to 16-bit DRAM], (D16=0, RAMSZ[1:0]=[1,X]). DMA Tern=minal Count goes high coincident
with nDACK for last transfer. See Page 72 for DMA Transfer Cycle Timing Parameters.
Row addr
Col Addr
Row Addr
Col Addr
Col Addr +1
Col Addr +2 Col Addr +3
System Bus Address
Data
Data
Data
MA[9:8]
SA[7:0]
nRAS
nCAS
DREQ
nDACK
SDBUS
nRD
nWR
Col Addr
System Bus Address
Data
Data
Data
Row Addr
Row Addr
Col Addr
Col Ad +1 Col Ad +2
MA[9:8]
SA[7:0]
nRAS
nCAS
DREQ
nDACK
SDBUS
nRD
nWR
TC



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