PPC34C60 datasheet(27/58 Pages) SMSC

27 / 58 page

SMSC DS – PPC34C60

Page 27

Rev. 06/01/2001

ADVANCED INFORMATION

CHIP REVISION LEVEL REGISTER - 1101 (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TYPE ID

REVISION

It is expected that the PPC34C60 will be used in various designs at different integration levels. This register provides a

means of determining which type of chip is in use. The most significant five bits are reserved for a Type ID; The least

significant three bits may be used to identify different masks and/or process types. This document refers to chips with

Revision Level values:

0000 0000

PORT TEST WRITE REGISTER - 1110 (Write Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INCREMENTING WRITE TEST PATTERN

The Port Test Write Register is used to determine the highest reliable printer port data transfer rate. An interface test must

be performed at various speeds until data integrity can be assured. To enable this test, select the Port Test Write Register

with an Address Write cycle. After being selected, the register looks for an incrementing pattern starting at 00. If data is

written out of sequence, or if a communications error occurs, the ERR bit in the Data Transfer Control Register will be set.

PORT TEST READ REGISTER - 1110 (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INCREMENTING READ TEST PATTERN

The Port Test Read Register verifies the read data transfer rate. To enable this test, select the Port Test Read Register

with an Address Write cycle. After being selected, this Register reads 00 when first addressed, and increments with every

access. The ERR bit in the Data Transfer Control Register is not affected by the Port Test Read.

DATA TRANSFER CONTROL REGISTER - 1111 (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ERR

rsvrd

BURST

8BIT

Bits 0 and 1 of this register provide options to regulate data transfer on non-enhanced ports. Bit 7 provides data transfer

rate status information as described in the Port Test Write Register.

Bit 7:ERR

This bit is set if an error occurs writing to the Port Test Write Register. It is cleared by selecting the Port Test Register with

an Address Write cycle.

Bits 6-2:rsvrd

These bits are reserved and should be written as zeros.

Bit 1:BURST

This bit is valid if the PPC34C60 is selected for Compatibility mode. Burst mode applies for reads and writes in Byte mode

and reads in Nibble mode (see IEEE STD 1284 - Reference 1). Setting this bit maximizes data transfer by minimizing

handshaking requirements. Data is latched on each edge of the Burst strobe as shown in FIGURE 5.

Bit 0:8BIT

This bit is only valid with a bi-directional port in Compatibility mode. Setting this bit selects Reverse Transfer Byte mode.

Clearing this bit selects Reverse Transfer Nibble mode (see IEEE STD 1284 - Reference 1).

PPC34C60 数据表(PDF) 27 Page - SMSC Corporation

PPC34C60 数据表(HTML) 27 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载

链接网址

PPC34C60 数据表(PDF) 27 Page - SMSC Corporation

PPC34C60 数据表(HTML) 27 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表 下载

链接网址

数据表下载