PPC34C60 datasheet(36/58 Pages) SMSC

36 / 58 page

SMSC DS – PPC34C60

Rev. 06/01/2001

ADVANCED INFORMATION

TIMING DIAGRAMS

The PPC34C60 supports three communications cycles: Address Write, Data Write, and Data Read. The signaling for these

cycles in Standard, EPP, and ECP modes is discussed below.

ADDRESS WRITE

An Address Write cycle must be issued before any Data cycles, since this tells the PPC34C60 whether the following Data

cycles are write/read, and where the data should go/come from.

Standard Mode

The host places the address information on the parallel port data lines, then strobes the address into the PPC34C60 by

pulsing Select In (HSEL) low with a minimum 200 ns pulse width. The PPC34C60 will always accept the Address Write

cycle, there is no Busy hold off.

EPP Mode

The host sends address information by writing to the EPP Address Register (base+3). The EPP interface chip places this

data on the parallel port data lines, then brings Select In (HSEL) low. The PPC34C60 latches the information, then

acknowledges the transfer by raising Busy (HBSY). The EPP interface chip may terminate the cycle when it sees Busy go

high.

ECP Mode

The host sends address information by writing to the ECP Address FIFO (base+0). The ECP interface chip places this data

on the parallel port data lines, sets Auto LF (HALF) low to indicate address information, then sets Strobe (HSTB) low to start

the transfer. The PPC34C60 acknowledges the cycle by raising Busy (HBSY). The ECP chip then raises Strobe. The

PPC34C60 latches the information, then sets Busy low.

DATA WRITE

The data write cycle is used to send data to the PPC34C60 registers, DRAM, or the remote system. A previous Address

Write cycle must have been sent to the PPC34C60 selecting Write, and the target of the write.

Standard Mode

If the PPC34C60 can accept data, busy (HBSY) will be low. The host places the data on the parallel port data lines, then

strobes the data into the PPC34C60 by pulsing Strobe (HSTB) low with a minimum 200 ns pulse width. If the PPC34C60 is

operating in the Burst Mode, then Strobe should only change state instead of pulsing low.

EPP Mode

If the PPC34C60 can accept data, Busy (HBSY) will be low. The host sends data by writing to the EPP Data Registers

(base+4 - base+7). The EPP interface chip places the data on the parallel port data lines, then lowers Auto LF (HALF).

The PPC34C60 latches the data, then raises Busy to acknowledge the transfer. The EPP interface chip may terminate the

cycle when it sees Busy go high.

ECP Mode

If the PPC34C60 can accept data, Busy (HBSY) will be low. The host sends data by writing to the ECP Data FIFO

(base+400h). The ECP interface chip places this data on the parallel port data lines, sets Auto LF (HALF) high to indicate

data cycle, then lowers Strobe (HSTB) to start the transfer. The PPC34C60 acknowledges the cycle by raising Busy. The

ECP chip then raises Strobe. The PPC34C60 latches the data, then sets Busy low.

DATA READ

A Data Read cycle is used to get data from the PPC34C60 registers, DRAM, or the remote system. A previous Address

Write cycle must have been sent to the PPC34C60 selecting Read, and the source of the read.

Standard Mode

If the PPC34C60 has data ready, Busy (HBSY) will be low. If the PPC34C60 is in 4 bit mode, the host reads the low nibble

from the status lines Ack (HACK), PError (HPE), Slct (HSLCT), Error (HERR). The host then pulses Strobe (HSTB) low to

acknowledge the low nibble. The PPC34C60 then places the high nibble on the same status lines, the host reads the high

nibble, then pulses Strobe to signal receipt of the data. If the PPC34C60 is in 8 bit mode, then the host disables it's data

drivers, floating the parallel port data lines. The host enables the PPC34C60 bus drivers by lowering Init (HINIT), reads the

data from the data lines, then pulses Strobe low to acknowledge the transfer. If the PPC34C60 is operating in Burst Mode,

then the Strobe only changes State instead of pulsing low in the above description.

EPP Mode

If the PPC34C60 has data ready, Busy (HBSY) will be low. The host gets data from the PPC34C60 by reading the EPP

Data Registers (base+4-base+7). The EPP interface chip disables the port drivers, then lowers Auto LF (HALF). At this

point, the PPC34C60 drives data onto the data lines, then raises Busy. The EPP Chip then latches the data, and raises

Auto LF to terminate the cycle.

PPC34C60 数据表(PDF) 36 Page - SMSC Corporation

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