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PPC34C60 数据表(PDF) 38 Page - SMSC Corporation |
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PPC34C60 数据表(HTML) 38 Page - SMSC Corporation |
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38 / 58 page ![]() SMSC DS – PPC34C60 Page 38 Rev. 06/01/2001 ADVANCED INFORMATION SPP ADDRESS WRITE TIMING (PARALLEL PORT SIGNALS) PARAMETER MIN TYP MAX UNITS t1 nINIT controls the direction of the parallel port when in SPP mode. NINIT deasserted to HD[0:7] released to high impedance by the PPC34C60. 84 [2 SCLK] 125 [3 SCLK] ns t2 The Host can now drive HD[0:7] with an address byte and then strobe it into the PPC34C60 by asserting the nSEL signal. This time represents the address setup time required by the PPC34C60. 125 [3 SCLK] ns t3 Typically the address written to the PPC34C60 is an instruction detailing the type of transfer to follow (i.e., Data Read/Write to DRAM, Bus, Register). Thus, once this address is received by the PPC34C60, it asserts the BSY signal to indicate that it is preparing for the upcoming transfer. This time represents the time for BSY to assert from the assertion of nSEL. 167 [4 SCLK] 208 [5 SCLK] ns t4 nSEL pulse width. This time represents the duration that nSEL must be asserted in order for the PPC34C60 to recognize an edge. 125 [3 SCLK] ns t5 The Host is required to hold the address valid for this amount of time following assertion of the nSEL line. 167 [4 SCLK] ns t6 nINIT controls the direction of the parallel port when in SPP mode. nINIT may be asserted anytime after the address hold time (t5) has been satisfied. This time represents the time from nINIT asserted to HD[0:7] driven by the PPC34C60. 84 [2 SCLK] 125 [3 SCLK] ns |
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