PPC34C60 datasheet(8/58 Pages) SMSC

8 / 58 page

SMSC DS – PPC34C60

Page 8

Rev. 06/01/2001

ADVANCED INFORMATION

DESCRIPTION OF PIN FUNCTIONS

PIN NO.

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

SYSTEM (REGENERATED ISA PERIPHERAL) INTERFACE

System

Clock/Crystal

XIN (SCLK)

XOUT

XIN may be connected to a ttl peripheral

system clock or a crystal may be placed

across XIN/XOUT (typically 24MHz).

This is used to derive the internal clock

(BUSCLK) used for all system interface

timing.

80-73

System

Address

[0:7]

SA[0:7]

These lower eight address bits are

presented to the system bus directly by

the PPC34C60 during bus and DRAM

access. Upper address bits, if needed,

should be latched through use of the

PPC34C60's

strobe

lines

prior

generating bus accesses.

70,69

Memory

Address

[8,9]

MA[8:9]

These address bits are appended to

SA[0:7] to create a 10-bit row or column

address for DRAM access.

68-61,

58-51

System Data [0:15] SD[0:15]

I/O8,

These bi-directional pins are used to

transfer data during bus or DRAM cycles

to or from the system.

nSystem Read

nSRD

This indicates that a bus read cycle is

occurring, similar to an ISA MEMR signal.

nSystem Write

nSWR

This indicates that a bus write cycle is

occurring, similar to an ISA MEMW

signal.

n16-Bit I/O

nIO16

I, PU

This signal is asserted by the remote

system to indicate whether or not the

address being accessed is capable of a

16-bit transfer.

Interrupt Request

IRQ

I, PU

This rising edge activated signal indicates

an interrupt request from the System.

nSystem Reset

nSRST

This low going signal can be used to

reset the System. This signal is asserted

for 16 SCLKs.

System Reset

SRST

This high going signal can be used to

reset the System. This signal is asserted

for 16 SCLKs.

nRow

Address

Strobe

nRAS

This low going strobe signal is used by

the DRAM to latch the row address,

present on the SA[0:7] and MA[8:9] pins.

This output drives the DRAM directly,

however

series

resistor

recommended on this line.

nColumn Address

Strobe

nCAS

This low going strobe signal is used by

the DRAM to latch the column address,

present on the SA[0:7] and MA[8:9] pins.

This output drives the DRAM directly,

however

series

resistor

recommended on this line.

nDMA

Acknowledge

nDACK

This active low output signal is issued to

inform the System that data is to be

transferred using DMA transfer cycles.

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