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PPC34C60 数据表(PDF) 54 Page - SMSC Corporation |
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PPC34C60 数据表(HTML) 54 Page - SMSC Corporation |
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54 / 58 page ![]() SMSC DS – PPC34C60 Page 54 Rev. 06/01/2001 ADVANCED INFORMATION FIGURE 24 - DRAM WRITE CYCLE TIMING When the DRAM bus width (4, 8 or 16 bits) is narrower than the Host bus (always 8-bits) or the Peripheral bus (8 or 16 bits) than the PPC34C60 will implement fast page mode DRAM cycles to complete the data transfer. These page mode transfers are performed for DMA as well as Host DRAM access. See DRAM Write Cycle Timing parameters. DRAM WRITE CYCLE TIMING PARAMETER MIN TYP MAX UNITS t1 10-bit DRAM row address valid to nWR asserted. 74 [1 BCLK -10] 84 [1 BCLK] 94 [1BCLK +10] ns t2 10-bit DRAM row address valid to nRAS asserted. 74 [1 BCLK -10] 84 [1 BCLK] 94 [1BCLK +10] ns t3 nRAS asserted to valid 10-bit DRAM column address. 74 [1 BCLK -10] 84 [1 BCLK] 94 [1BCLK +10] ns t4 10-bit DRAM column address valid to nCAS asserted. 74 [1 BCLK -10] 84 [1 BCLK] 94 [1BCLK +10] ns t5 10-bit DRAM column address incremented following nCAS asserted. 74 [1 BCLK -10] 84 [1 BCLK] 94 [1BCLK +10] ns t6 Valid write data in relation to the 10-bit column address presented by the PPC34C60. 0 10 ns t7 DRAM column address incremented to nCAS deasserted. 74 [1 BCLK -10] 84 [1 BCLK] 94 [1BCLK +10] ns t8 Valid write data in relation to the 10-bit column address presented by the PPC34C60. 0 10 ns t9 nCAS deasserted to valid data placed on the data bus. 0 10 ns t10 nCAS and nRAS both deasserted to nWR deasserted. 0 42 [1 SCLK] ns t3 t5 t4 t7 t2 t1 t10 t6 t8 t9 t8 Data Valid Row Addr Row Addr Col Addr Col Addr +2 Col Addr +1 SAB Data Valid Col Addr bits 8 & 9 SAB MA[8:9] SA[0:7] nCAS nRAS nRD nWR SD[0:15] BUSCLK |
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