数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

PPC34C60 数据表(PDF) 54 Page - SMSC Corporation

部件名 PPC34C60
功能描述  PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
PDF  58 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

PPC34C60 数据表(HTML) 54 Page - SMSC Corporation

Back Button PPC34C60 Datasheet HTML 50Page - SMSC Corporation PPC34C60 Datasheet HTML 51Page - SMSC Corporation PPC34C60 Datasheet HTML 52Page - SMSC Corporation PPC34C60 Datasheet HTML 53Page - SMSC Corporation PPC34C60 Datasheet HTML 54Page - SMSC Corporation PPC34C60 Datasheet HTML 55Page - SMSC Corporation PPC34C60 Datasheet HTML 56Page - SMSC Corporation PPC34C60 Datasheet HTML 57Page - SMSC Corporation PPC34C60 Datasheet HTML 58Page - SMSC Corporation  
Zoom Inzoom in Zoom Outzoom out
 54 / 58 page
background image
SMSC DS – PPC34C60
Page 54
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 24 - DRAM WRITE CYCLE TIMING
When the DRAM bus width (4, 8 or 16 bits) is narrower than the Host bus (always 8-bits) or the Peripheral bus (8 or 16 bits)
than the PPC34C60 will implement fast page mode DRAM cycles to complete the data transfer. These page mode
transfers are performed for DMA as well as Host DRAM access.
See DRAM Write Cycle Timing parameters.
DRAM WRITE CYCLE TIMING
PARAMETER
MIN
TYP
MAX
UNITS
t1
10-bit DRAM row address valid to nWR
asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t2
10-bit DRAM row address valid to nRAS
asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t3
nRAS asserted to valid 10-bit DRAM
column address.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t4
10-bit DRAM column address valid to
nCAS asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t5
10-bit DRAM column address incremented
following nCAS asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t6
Valid write data in relation to the 10-bit
column
address
presented
by
the
PPC34C60.
0
10
ns
t7
DRAM column address incremented to
nCAS deasserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t8
Valid write data in relation to the 10-bit
column
address
presented
by
the
PPC34C60.
0
10
ns
t9
nCAS deasserted to valid data placed on
the data bus.
0
10
ns
t10
nCAS and nRAS both deasserted to nWR
deasserted.
0
42
[1 SCLK]
ns
t3
t5
t4
t7
t2
t1
t10
t6
t8
t9
t8
Data Valid
Row Addr
Row Addr
Col Addr
Col Addr +2
Col Addr +1
SAB
Data Valid
Col Addr bits 8 & 9
SAB
MA[8:9]
SA[0:7]
nCAS
nRAS
nRD
nWR
SD[0:15]
BUSCLK



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com