PPC34C60 datasheet(46/58 Pages) SMSC

46 / 58 page

SMSC DS – PPC34C60

Page 46

Rev. 06/01/2001

ADVANCED INFORMATION

FIGURE 17 - EPP DATA READ TIMING (PARALLEL PORT SIGNALS)

See EPP Data Read Timing Parameters.

EPP DATA READ TIMING (PARALLEL PORT SIGNALS)

PARAMETER

MIN

TYP

MAX

UNITS

The Host deasserts nSTB to indicate that

the forthcoming transfer is a read cycle. At

the same time or soon after the Host will

release the Parallel port data lines HD[0:7]

to a high impedance state. This specifies

the time between nSTB being asserted and

an address appearing on HD[0:7].The

PPC34C60 does not rely on nSTB.

After tri-stating the HD[0:7] lines, the Host

then

asserts

nALF

inform

the

PPC34C60 that a data cycle is taking

place.

The PPC34C60 will respond by placing

data on HD[0:7].

125

[3 SCLK]

1,084

[13 BCLK]

Then the PPC34C60 will assert the BSY

line to inform the Host that it has placed a

valid byte of data on the parallel port data

lines HD[0:7].

125

[3 SCLK]

167

[4 SCLK]

Next, the Host latches the data on HD[0:7]

and deasserts nALF to inform the

PPC34C60 that the cycle is complete.

[SCLK]

In response, the PPC34C60 tri-states the

parallel port data lines HD[0:7].

209

[5 SCLK]

After tri-stating HD[0:7] the PPC34C60

deassert BSY to indicate that it is now

ready for the next EPP transfer.

[SCLK]

As soon as the PPC34C60 deasserts BSY

the Host may initiate another EPP transfer.

This time represents the time between the

PPC34C60 deasserting BSY to the Host

starting a new transfer cycle.

VALID DATA

HD[0:7]

nSTB H

nALF H

nSEL H

nINIT H

BSY P

nACK P

PE P

SLCT P

nERR P

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