PPC34C60 datasheet(29/58 Pages) SMSC

29 / 58 page

SMSC DS – PPC34C60

Page 29

Rev. 06/01/2001

ADVANCED INFORMATION

DRAM BUFFER OPERATION

The PPC34C60 provides support for a DRAM buffer with DMA capability. DRAM bus widths of 4, 8, or 16 bits may be

used, with linear 20 bit addressing. DMA to and from the DRAM may be either 8 or 16 bit cycles. The PPC34C60 will take

care of matching the bus widths between the DMA Controller and the DRAM. If multiple DRAM accesses are necessary for

a DMA cycle, they will use fast page mode.

DRAM refresh is automatic, and uses a CAS before RAS refresh method. The DRAM is addressed as a number of

buffers. The buffer size is programmable to 'power of 2' sizes between 2 and 64K bytes. A byte counter is used to

control the DRAM access. It may be programmed to any value from 1 up to the buffer size. To prevent overwriting data,

the byte counter should not be set to a value exceeding the buffer size.

The DRAM may be independently accessed by the host and the DMA Controller. There are separate buffer and byte

counters for each. When a DRAM transfer is complete, the buffer number is incremented, and further DRAM access is

blocked.

DRAM Linear Address Mapping

MA9

MA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

ROW

A19

A17

A15

A14

A13

A12

A11

A10

COL

A18

A16

64K x N

256K x N

1M x N

PPC34C60 数据表(PDF) 29 Page - SMSC Corporation

PPC34C60 数据表(HTML) 29 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载