PPC34C60 datasheet(18/58 Pages) SMSC

18 / 58 page

SMSC DS – PPC34C60

Page 18

Rev. 06/01/2001

ADVANCED INFORMATION

3.4 Internal Register Map

The internal registers of the PPC34C60 are selected by performing an Address Write Cycle with bits B and M (bits 5 and 4)

set to 1,1 (see Table 2). The desired register is selected by the binary value of A3A2A1A0 (bits-3:0), also shown as

RRRR. Internal register RRRR is made available for Read or Write based on the bit value of W (bit 6) as shown below. All

internal registers are eight bits wide.

Table 3 - Internal Register Map

RRRR

DEFAULTS

0000

Address Register

0001

Output Configuration Reg

0010

Output Register

0011

Sound Register

0011

Input Register

0100

Operation Register

0101

DRAM Buffer Size Register

0110

Host DRAM Buffer Pointer

0111

DMA DRAM Buffer Pointer

1000

Host Max Block Count - Low

1001

Host Max Block Count - High

1010

DMA Byte Count - Low

1011

DMA Byte Count - High

1100

Configuration Register

1101

Chip Revision Level

1110

Port Test Register

1110

Port Test Register

1111

Data Transfer Control Register

X = Read/Write

1 = Write

0 = Read

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