PPC34C60 datasheet(32/58 Pages) SMSC

32 / 58 page

SMSC DS – PPC34C60

Page 32

Rev. 06/01/2001

ADVANCED INFORMATION

Table 6 - DRAM Refresh State Flow Description*

IDLE

nRAS and nCAS go inactive.

STATE 1

nCAS goes active for first refresh.

STATE 2

nRAS goes active for first refresh.

STATE 3

STATE 4

nRAS and nCAS go inactive.

STATE 5

nCAS goes active for second refresh.

STATE 6

nRAS goes active for second refresh.

STATE 7

*For SCLK = 24 MHz, a DRAM Refresh Cycle is performed every 30

µS. Bus cycles have built-in DRAM refresh which

reset the 30

µS refresh timer.

POWERING THE PPC34C60

The PPC34C60 has a built-in mechanism to insure against damage when the peripheral is powered down and the host is

powered up.

FIGURE 8 shows how to incorporate this protection feature into your peripheral's power and return design. Isolate the

chip's VCC from the rest of the peripheral's VCC using a Schottky diode. The SENSE input should be tied to the

peripheral's VCC and the anode of the diode. When the peripheral's power is off, the SENSE input will go low, tri-stating all

outputs. This prevents the PPC34C60 from driving into a low impedance load and damaging its input protection diodes.

When the peripheral's power is turned on, the SENSE line will be pulled high and all output drivers of the PPC34C60 will be

enabled.

FIGURE 8 - SUGGESTED PP

PPC34C60

Schottky diode, Vrb > 10v

1N5818 - Under 1 Amp

1N5821 - 1-3 Amps

Power Supply

VCC

SENSE

VCC

GND

To VCC for the

rest of the system.

PPC34C60 数据表(PDF) 32 Page - SMSC Corporation

PPC34C60 数据表(HTML) 32 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载