TNETV1644ZDU6 datasheet(231/306 Pages) TI1

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VCLK

(Positive Edge

Clocking)

VCLK

(Negative Edge

Clocking)

VCTL(B)

VDATA(C)

VCLKIN(A)

A. VCLKIN = PCLK or VPBECLK

B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE

C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 6-45. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to VCLK(1)(2)(3) (see Figure 6-26)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

PARAMETER

UNIT

MIN

MAX

tc(VCLK)

Cycle time, VCLK

13.33

160

tw(VCLKH)

Pulse duration, VCLK high

0.4C

tw(VCLKL)

Pulse duration, VCLK low

0.4C

tt(VCLK)

Transition time, VCLK

td(VCLKINH-VCLKH)

Delay time, VCLKIN high to VCLK high

td(VCLKINL-VCLKL)

Delay time, VCLKIN low to VCLK low

td(VCLK-VCTLV)

Delay time, VCLK edge to VCTL valid

td(VCLK-VCTLIV)

Delay time, VCLK edge to VCTL invalid

0.6

td(VCLK-VDATAV)

Delay time, VCLK edge to VDATA valid

td(VCLK-VDATAIV)

Delay time, VCLK edge to VDATA invalid

0.6

(1)

The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the

rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.

(2)

VCLKIN = PCLK or VPBECLK

(3)

C = VCLK period in ns.

Figure 6-26. VPBE Control and Data Output Timing With Respect to VCLK

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