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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2-Auto 数据表(PDF) 128 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 128 Page - STMicroelectronics |
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128 / 371 page  Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 128/371 Figure 54. Serial peripheral interface block diagram Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure 55. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 58 on page 132) but master and slave must be programmed with the same timing mode. SPIDR Read buffer 8-bit shift register Write Read Data/address bus SPI state control SPIE SPE MSTR CPHA SPR0 SPR1 CPOL Serial clock generator MOSI MISO SS SCK SPICR SPICSR Interrupt request Master control SPR2 0 7 0 7 SPIF WCOL MODF 0 OVR SSI SSM SOD SOD bit SS 1 0 Obsolete Product(s) - Obsolete Product(s) |
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