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ST7MC1K2-Auto 数据表(PDF) 129 Page - STMicroelectronics

部件名 ST7MC1K2-Auto
功能描述  Clock, reset and supply management
PDF  371 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7MC1K2-Auto 数据表(HTML) 129 Page - STMicroelectronics

Back Button ST7MC1K2-Auto Datasheet HTML 125Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 126Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 127Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 128Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 129Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 130Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 131Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 132Page - STMicroelectronics ST7MC1K2-Auto Datasheet HTML 133Page - STMicroelectronics Next Button
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
On-chip peripherals
129/371
Figure 55.
Single master/single slave application
Slave select management
As an alternative to using the SS pin to control the slave select signal, the application can choose to
manage the slave select signal by software. This is configured by the SSM bit in the SPICSR register
(see Figure 57).
In software management, the external SS pin is free for other application uses and the internal SS signal
level is driven by writing to the SSI bit in the SPICSR register.
In master mode SS internal must be held high continuously.
In slave mode, there are two cases depending on the data/clock timing relationship (see Figure 56):
If CPHA = 1 (data latched on second clock edge)
SS internal must be held low during the entire transmission. This implies that in single slave
applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS
function by software (SSM = 1 and SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge)
SS internal must be held low during byte transmission and pulled high between each byte to allow
the slave to write to the shift register. If SS is not pulled high, a write collision error occurs when the
slave writes to the shift register (see Write collision error (WCOL) on page 133).
Figure 56.
Generic SS timing diagram
8-bit shift register
SPI clock
generator
8-bit shift register
MISO
MOSI
MOSI
MISO
SCK
SCK
Slave
Master
SS
SS
+5V
MSBit
LSBit
MSBit
LSBit
Not used if SS is managed
by software
MOSI/MISO
Master SS
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Byte 2
Byte 1Byte 3
Obsolete
Product(s)
- Obsolete
Product(s)



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