ST7MC1K2-Auto datasheet(130/371 Pages) STMICROELECTRONICS

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Figure 57.

Hardware/software slave select management

Master mode operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and

phase are configured by software (refer to SPI control/status register (SPICSR) on

page 137).

Note:

The idle state of SCK must correspond to the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

To operate the SPI in master mode, perform the following steps in order:

Write to the SPICR register:

–

Select the clock frequency by configuring the SPR[2:0] bits.

–

Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.

Figure 58 shows the four possible configurations.

Note:

The slave must have the same CPOL and CPHA settings as the master.

Write to the SPICSR register:

–

Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin

high for the complete byte transmit sequence.

Write to the SPICR register:

–

Set the MSTR and SPE bits

Note:

MSTR and SPE bits remain set only if SS is high).

Caution:

If the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not

taken into account.

The transmit sequence begins when software writes a byte in the SPIDR register.

Master mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

When data transfer is complete:

●

The SPIF bit is set by hardware.

●

An interrupt request is generated if the SPIE bit is set and the interrupt mask in the

CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

An access to the SPICSR register while the SPIF bit is set

A read to the SPIDR register

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

SS internal

SSM bit

SSI bit

SS external pin

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