ST7MC1K2-Auto datasheet(167/371 Pages) STMICROELECTRONICS

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Figure 71.

LDIV read/write operations when LDUM = 1

LINSCI clock tolerance

LINSCI clock tolerance when unsynchronized

When LIN slaves are unsynchronized (meaning no characters have been transmitted for a

relatively long time), the maximum tolerated deviation of the LINSCI clock is

±15%.

If the deviation is within this range then the LIN synch break is detected properly when a

new reception occurs.

This is made possible by the fact that masters send 13 low bits for the LIN synch break,

which can be interpreted as 11 low bits (13 bits - 15% = 11.05) by a ‘fast’ slave and then

considered as a LIN synch break. According to the LIN specification, a LIN synch break is

valid when its duration is greater than tSBRKTS = 10. This means that the LIN synch break

must last at least 11 low bits.

Note:

If the period desynchronization of the slave is +15% (slave too slow), the character ‘00h’

which represents a sequence of 9 low bits must not be interpreted as a break character

(9 bits + 15% = 10.35). Consequently, a valid LIN synch break must last at least 11 low bits.

LINSCI clock tolerance when synchronized

When synchronization has been performed, following reception of a LIN synch break, the

LINSCI, in LIN mode, has the same clock deviation tolerance as in SCI mode, which is

explained below:

During reception, each bit is oversampled 16 times. The mean of the 8th, 9th and 10th

samples is considered as the bit value.

Consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit.

The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one

start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%.

RDRF = 1

Write LPR

Write LPFR

LDIV_NOM

FRAC(3:0)

MANT(7:0)

LIN sync field

measurement

Update

at end of

synch field

MANT(7:0)

FRAC(3:0)

LDIV_MEAS

MANT(7:0)

LDIV

FRAC(3:0)

Baud rate generation

Read LPR

Read LPFR

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