T48C862-R4 datasheet(63/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Timer 3 Control Register 1

(T3C) Write

Primary register address: "C"hex - Write

Timer 3 Status Register 1

(T3ST) Read

Primary register address: "C"hex - Read

Note:

The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.

Bit 3Bit 2Bit 1Bit 0

Write

T3EIM

T3TOP

T3TS

T3R

Reset value: 0000b

T3EIM

imer 3 Edge Interrupt Mask

T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)

T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)

T3TOP

imer 3 Toggle Output Preset

T3TOP = 0, sets toggle output (M3) to "0"

T3TOP = 1, sets toggle output (M3) to "1"

Note: If T3R = 1, no output preset is possible

T3TS

imer 3 Toggle with Start T3TS = 0, Timer 3 output is not toggled during the start

T3TS = 1, Timer 3 output is toggled if started with T3R

T3R

imer 3 Run

T3R = 0, Timer 3 stop and reset

T3R = 1, Timer 3 run

Bit 3Bit 2Bit 1Bit 0

Read

–

T3ED

T3C2

T3C1

Reset value: x000b

T3ED

imer 3 Edge Detect

This bit will be set by the edge-detect logic of Timer 3 input (T3I)

T3C2

imer 3 Compare 2

This bit will be set when a match occurs between Counter 3 and T3CO2

T3C1

imer 3 Compare 1

This bit will be set when a match occurs between Counter 3 and T3CO1

T48C862-R4 数据表(PDF) 63 Page - ATMEL Corporation

T48C862-R4 数据表(HTML) 63 Page - ATMEL Corporation

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