T48C862-R4 datasheet(69/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Before data can be transferred, the SSI must first be activated. This is performed by

means of the SSI reset control (SIR) bit. All further operation then depends on the data

directional mode (TX/RX) and the present status of the SSI buffer registers shown by

the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the

(empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX

mode). The control logic ensures that data shifting is temporarily halted at any time, if

the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will

then automatically be set back to ‘1’ and data shifting resumed as soon as the applica-

tion software loads the new data into the transmit register (in TX mode) or frees the shift

A further activity status (ACT) bit indicates the present status of the serial communica-

tion. The ACT bit remains high for the duration of the serial telegram or if MCL stop or

start conditions are currently being generated. Both the current SRDY and ACT status

can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set

high.

8-bit Synchronous Mode

Figure 65.

8-bit Synchronous Mode

In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface

(see “SSI Peripheral Configuration” on page 67). The serial data (SD) is received or

transmitted in NRZ format, synchronized to either the rising or falling edge of the shift

clock (SC). The choice of clock edge is defined by the Serial Mode Control bits

(SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge

with which the SD changes. To avoid clock skew problems, the incoming serial input

data is shifted in with the opposite edge.

When used together with one of the timer modulator or demodulator stages, the SSI

must be set in the 8-bit synchronous mode 1.

In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and

the incoming serial data is shifted into the shift register. This first telegram is automati-

cally transferred into the receive buffer and the SRDY set to 0 indicating that the receive

buffer contains valid data. At the same time an interrupt (if enabled) is generated. The

SSI then continues shifting in the following 8-bit telegram. If, during this time the first

telegram has been read by the controller, the second telegram will also be transferred in

the same way into the receive buffer and the SSI will continue clocking in the next tele-

gram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI

will stop, temporarily holding the second telegram in the shift register until a certain point

of time when the controller is able to service the receive buffer. In this way no data is lost

or overwritten.

DATA

SD/TO2

Bit 7

Bit 0

Bit 7

Bit 0

Data: 00110101

(Rising edge)

(Falling edge)

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