T48C862-R4 datasheet(72/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Figure 69.

Example of MCL Receive Dialog

8-bit Pseudo MCL Mode

In this mode, the SSI exhibits all the typical MCL operational features except for the

acknowledge bit which is never expected or transmitted.

MCL Bus Protocol

The MCL protocol constitutes a simple 2-wire bi-directional communication highway via

which devices can communicate control and data information. Although the MCL proto-

col can support multi-master bus configurations, the SSI in MCL mode is intended for

use purely as a master controller on a single master bus system. So all reference to

multiple bus control and bus contention will be omitted at this point.

All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge bit.

Normally the communication channel is opened with a so-called start condition, which

initializes all devices connected to the bus. This is then followed by a data telegram,

transmitted by the master controller device. This telegram usually contains an 8-bit

address code to activate a single slave device connected onto the MCL bus. Each slave

receives this address and compares it with its own unique address. The addressed

slave device, if ready to receive data, will respond by pulling the SD line low during the

9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting

this affirmative acknowledge then opens a connection to the required slave. Data can

then be passed back and forth by the master controller, each 8-bit telegram being

acknowledged by the respective recipient. The communication is finally closed by the

master device and the slave device put back into standby by applying a stop condition

onto the bus.

7 6 54 32 1

7 6 5 43 21 0 A

msb

lsb

tx data 1

rx data 2

msb

lsb

Write STB

(tx data 1)

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

Read SRB

(rx data 2)

SIR

SDD

Start

Stop

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