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T48C862-R4 数据表(PDF) 36 Page - ATMEL Corporation |
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T48C862-R4 数据表(HTML) 36 Page - ATMEL Corporation |
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36 / 107 page ![]() 36 T48C862-R4 [Preliminary] 4551C–4BMCU–01/04 Figure 30. Bi-directional Port 5 Figure 31. Port 5 External Interrupts Port 5 Data Register (P5DAT) Primary register address: "5"hex Port 5 Control Register (P5CR) Byte Write Auxiliary register address: "5"hex P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code Master reset Q V DD BP5y Configurable * * P5DATy I/O Bus D IN enable I/O Bus * * Switched pull-up Switched pull-down * Static pull-up (Data out) * * S * V DD Static Pull-down V DD Bidir. Port Data in IN_Enable BP53 P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1 Decoder Decoder Decoder Decoder Bidir. Port Data in IN_Enable BP52 I/O-bus Bidir. Port Data in IN_Enable BP51 I/O-bus Bidir. Port Data in IN_Enable BP50 INT1 INT6 P5CR: Bit 3Bit 2Bit 1Bit 0 P5DAT3 P5DAT2 P5DAT1 P5DAT0 Reset value: 1111b Bit 3Bit 2Bit 1Bit 0 First write cycle P51M2 P51M1 P50M2 P50M1 Reset value: 1111b Bit 7Bit 6Bit 5Bit 4 Second write cycle P53M2 P53M1 P52M2 P52M1 Reset value: 1111b |
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