T48C862-R4 datasheet(73/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Figure 70.

MCL Bus Protocol 1

Bus not busy (1)

Both data and clock lines remain HIGH.

Start data transfer (2)

A HIGH to LOW transition of the SD line while the clock (SC)

is HIGH defines a START condition.

Stop data transfer (3)

A LOW to HIGH transition of the SD line while the clock (SC)

is HIGH defines a STOP condition.

Data valid (4)

The state of the data line represents valid data when,

after START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

Acknowledge

All address and data words are serially transmitted to and

from the device in eight-bit words. The receiving device

returns a zero on the data line during the ninth clock cycle to

acknowledge word receipt.

Figure 71.

MCL Bus Protocol 2

(2)

(1)

(4)

(3)

(1)

Start

condition

Data

valid

Data

change

Data

valid

Stop

condition

Start

1st Bit

8th Bit

ACK

Stop

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