T48C862-R4 datasheet(17/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

RAM Address Registers

The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y.

These registers allow access to any of the 256 RAM nibbles.

Expression Stack Pointer (SP)

The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the

expression stack. The pointer is automatically pre-incremented if a nibble is moved onto

the stack or post-decremented if a nibble is removed from the stack. Every post-decre-

ment operation moves the item (TOS-1) to the TOS register before the SP is

decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate

the start address of the expression stack area.

Return Stack Pointer (RP)

The return stack pointer points to the top element of the 12-bit wide return stack. The

pointer automatically pre-increments if an element is moved onto the stack, or it post-

decrements if an element is removed from the stack. The return stack pointer incre-

ments and decrements in steps of 4. This means that every time a 12-bit element is

stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH

compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial-

ized via >RP FCh.

RAM Address Registers

(X and Y)

The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation

moves the addressed nibble onto the TOS. A store operation moves the TOS to the

addressed RAM location. By using either the pre-increment or post-decrement address-

ing mode arrays in the RAM can be compared, filled or moved.

Top of Stack (TOS)

The top of stack register is the accumulator of the microcontroller block. All arith-

metic/logic, memory reference and I/O operations use this register. The TOS register

receives data from the ALU, EEPROM, RAM or I/O bus.

Condition Code Register

(CCR)

The 4-bit wide condition code register contains the branch, the carry and the interrupt

enable flag. These bits indicate the current state of the CPU. The CCR flags are set or

reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow

direct manipulation of the condition code register.

Carry/Borrow (C)

The carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit

(ALU) occurred during the last arithmetic operation. During shift and rotate operations,

this bit is used as a fifth bit. Boolean operations have no effect on the C-flag.

Branch (B)

The branch flag controls the conditional program branching. Should the branch flag has

been set by a previous instruction, a conditional branch will cause a jump. This flag is

affected by arithmetic, logic, shift, and rotate operations.

Interrupt Enable (I)

The interrupt enable flag globally enables or disables the triggering of all interrupt rou-

tines with the exception of the non-maskable reset. After a reset or while executing the

DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will

not accept any further interrupt requests until the interrupt enable flag has been set

again by either executing an EI or SLEEP instruction.

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