T48C862-R4 datasheet(64/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Timer 3 Clock Select Register

(T3CS)

Address: "B"hex - Subaddress: "1"hex

Table 22.

Timer 3 Edge Select Bits

Table 23.

Timer 3 Clock Select Bits

Timer 3 Compare- and

Compare-mode Register

Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of

Timer 3. The timer compares the content of the compare register with the current

counter value. If both match, it generates a signal. This signal can be used for the

counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock

or as clock for the next counter stage. For each compare register, a compare-mode reg-

ister exists. These registers contain mask bits to enable or disable the generation of an

interrupt, a counter reset, or an output toggling with the occurrence of a compare match

of the corresponding compare register. The mask bits for activating the single-action

mode can also be located in the compare mode registers. When assigned to the com-

pare register a compare event will be suppressed.

Bit 3

Bit 2

Bit 1

Bit 0

T3CS

T3E1

T3E0

T3CS1

T3CS0

Reset value: 1111b

T3E1

imer 3 Edge select bit 1

T3E0

imer 3 Edge select bit 0

T3E1

T3E0

Timer 3 Input Edge Select (T3I)

–

Positive edge at T3I pin

Negative edge at T3I pin

Each edge at T3I pin

T3CS1 T

imer 3 Clock Source select bit 1

T3CS0 T

imer 3 Clock Source select bit 0

T3CS1

TCS0

Counter 3 Input Signal (CL3)

System clock (SYSCL)

Output signal of Timer 2 (POUT)

Output signal of Timer 1 (T1OUT)

External input signal from T3I edge detect

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