T48C862-R4 datasheet(31/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Figure 27.

Example of I/O Addressing

Module ASW

Module M1

Module M2

Module M3

Auxiliary Switch

Module

Primary Reg.

(Address Pointer)

Subaddress Reg.

Bank of

Primary Reg.

to other modules

Subport Fh

Subport Eh

Subport 1

Subport 0

Primary Reg.

Aux. Reg.

Primary Reg.

I/O bus

Example of

qFORTH

program code

Indirect Subport Access

(Subport Register Write)

1 Addr. (SPort) Addr. (M1) OUT

2 SPort _Data

Addr. (M1) OUT

(Subport Register Read)

1 Addr. (SPort) Addr. (M1) OUT

Addr. (M1)

(Subport Register Write Byte)

1 Addr. (SPort) Addr. (M1)

OUT

(Subport Register Read Byte)

1 Addr. (SPort) Addr. (M1) OUT

Addr. (M1) IN (hi)

Addr. (M1) IN (lo)

Prim._Data Addr. (M2)

OUT

4 Addr. (M2) Addr. (ASW) OUT

Dual Register Access

(Primary Register Write)

(Auxiliary Register Write)

Aux._Data

Addr. (M2)

OUT

(Primary Register Read)

Addr. (M2)

(Auxiliary Register Read)

Addr. (M2)

(Auxiliary Register Write Byte)

Addr. (M2)

Addr. (ASW)

OUT

Aux._Data (lo) Addr. (M2)

OUT

Aux._Data (hi) Addr. (M2)

OUT

6 Prim._Data Addr.(M3) OUT

Single Register Access

(Primary Register Write)

Addr. (M3)

(Primary Register Read)

2 SPort _Data(lo) Addr. (M1) OUT

2 SPort _Data(hi) Addr. (M1) OUT

Addr.(ASW)

= Auxiliary Switch Module address

Addr.(Mx)

= Module Mx address

Addr.(SPort)

= Subport address

Prim._Data

= Data to be written into Primary Register

Aux._Data

= Data to be written into Auxiliary Register

Prim._Data(lo) = Data to be written into Auxiliary Register (low nibble)

Prim._Data(hi)

= Data to be written into Auxiliary Register (high nibble)

SPort_Data(lo) = Data to be written into SubPort (low nibble)

SPort_Data(hi) = Data to be written into SubPort (high nibble)

(lo) = SPort_Data (low nibble)

(hi) = SPort_Data (high nibble)

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