T48C862-R4 datasheet(42/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Timer 1 Control Register 1

(T1C1)

Address: "7"hex - Subaddress: "8"hex

* Bit 3 -> MSB, Bit 0 -> LSB

The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval

depends on this divider and the Timer 1 input clock source. The timer input can be sup-

plied by the system clock, the 32-kHz oscillator or via the clock management. If the clock

management generates the SUBCL, the selected input clock from the RC oscillator, 4-

MHz oscillator or an external clock is divided by 16.

Table 14.

Timer 1 Control Bits

Bit 3 *

Bit 2

Bit 1

Bit 0

T1RM

T1C2

T1C1

T1C0

Reset value: 1111b

T1RM

imer 1 Restart Mode T1RM = 0, write access without Timer 1 restart

T1RM = 1, write access with Timer 1 restart

Note:

If WDL = 0, Timer 1 restart is impossible

T1C2

imer 1 Control bit 2

T1C1

imer 1 Control bit 1

T1C0

imer 1 Control bit 0

T1C2

T1C1

T1C0

Divider

Time Interval with

SUBCL

Time Interval with

SUBCL = 32 kHz

Time Interval with

SYSCL = 2/1 MHz

SUBCL/2

61 µs

1 µs/2 µs

SUBCL/4

122 µs

2 µs/4 µs

SUBCL/8

244 µs

4 µs/8 µs

SUBCL/16

488 µs

8 µs/16 µs

SUBCL/32

0.977 ms

16 µs/32 µs

256

SUBCL/256

7.812 ms

128 µs/256 µs

2048

SUBCL/2048

62.5 ms

1024 µs/2048 µs

16384

SUBCL/16384

500 ms

8192 µs/16384 µs

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