T48C862-R4 datasheet(53/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Timer 2 Compare Mode

Address: "7"hex - Subaddress: "3"hex

Table 20.

Timer 2 Toggle Mask Bits

Timer 2 COmpare Register 1

(T2CO1)

Address: "7"hex - Subaddress: "4"hex

In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.

Timer 2 COmpare Register 2

(T2CO2) Byte Write

Address: "7"hex - Subaddress: "5"hex

Bit 3Bit 2Bit 1Bit 0

T2OTM

T2CTM

T2RM

T2IM

Reset value: 0000b

T2OTM

imer 2 Overflow Toggle Mask bit

T2OTM = 0, disable overflow toggle

T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output

flip-flop (TOG2). If the T2OTM bit is set, only a counter overflow can

generate an interrupt except on the Timer 2 output mode 7.

T2CTM

imer 2 Compare Toggle Mask bit

T2CTM = 0, disable compare toggle

T2CTM = 1, enable compare toggle, a match of the counter with the compare

when the T2CTM bit is set, only a match of the counter with the

compare register can generate an interrupt.

T2RM

imer 2 Reset Mask bit

T2RM = 0, disable counter reset

T2RM = 1, enable counter reset, a match of the counter with the compare register

resets the counter

T2IM

imer 2 Interrupt Mask bit

T2IM = 0, disable Timer 2 interrupt

T2IM = 1, enable Timer 2 interrupt

Timer 2 Output Mode

T2OTM

T2CTM

Timer 2 Interrupt Source

1, 2, 3, 4, 5 and 6

Compare match (CM2)

1, 2, 3, 4, 5 and 6

Overflow (OVF2)

Compare match (CM2)

Write cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: 1111b

First write cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: 1111b

Second write cycle

Bit 7

Bit 6

Bit 5

Bit 4

Reset value: 1111b

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