T48C862-R4 datasheet(55/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Timer 3 consists of an 8-bit up-counter with two compare registers and one capture reg-

ister. The timer can be used as event counter, timer and signal generator. Its output can

be programmed as modulator and demodulator for the serial interface. The two com-

pare re gisters enab le vario us mod es of signal gen eratio n, m odulatio n an d

demodulation. The counter can be driven by internal and external clock sources. For

external clock sources, it has a programmable edge-sensitive input which can be used

as counter input, capture signal input or trigger input. This timer input is synchronized

with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-

Stop -> yes), this timer input is stopped too. The counter is readable via its capture reg-

ister while it is running. In capture mode, the counter value can be captured by a

programmable capture event from the Timer 3 input or Timer 2 output.

A special feature of this timer is the trigger- and single-action mode. In trigger mode, the

counter starts counting triggered by the external signal at its input. In single-action

mode, the counter counts only one time up to the programmed compare match event.

These modes are very useful for modulation, demodulation, signal generation, signal

measurement and phase controlling. For phase controlling, the timer input is protected

against negative voltages and has zero-cross detection capability.

Timer 3 has a modulator output stage and input functions for demodulation. As modula-

tor it works together with Timer 2 or the serial interface. When the shift register is used

for modulation the data shifted out of the register is encoded bitwise. In all demodulation

modes, the decoded data bits are shifted automatically into the shift register.

Timer/Counter Modes

Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via

the Timer 3 Mode Register T3M.

In all these modes, the compare register and the compare-mode register belonging to it

define the counter value for a compare match and the action of a compare match. A

match of the current counter value with the content of one compare register triggers a

counter reset, a Timer 3 interrupt or the toggling of the output flip-flop. The compare

mode registers T3M1 and T3M2 contain the mask bits for enabling or disabling these

actions.

The counter can also be enabled to execute single actions with one or both compare

registers. If this mode is set the corresponding compare match event is generated only

once after the counter start.

Most of the timer modes use their compare registers alternately. After the start has been

activated, the first comparison is carried out via the compare register 1, the second is

carried out via the compare register 2, the third is carried out again via the compare reg-

ister 1 and so on. This makes it easy to generate signals with constant periods and

variable duty cycle or to generate signals with variable pulse and space widths.

If single-action mode is set for one compare register, the comparison is always carried

out after the first cycle via the other compare register.

The counter can be started and stopped via the control register T3C. This register also

controls the initial level of the output before start. T3C contains the interrupt mask for a

T3I input interrupt.

Via the Timer 3 clock-select register, the internal or external clock source can be

selected. This register selects also the active edge of the external input. An edge at the

external input T3I can generate also an interrupt if the T3EIM bit is set and the Timer 3 is

stopped (T3R = 0) in the T3C register.

T48C862-R4 数据表(PDF) 55 Page - ATMEL Corporation

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