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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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T48C862-R4 数据表(PDF) 70 Page - ATMEL Corporation |
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T48C862-R4 数据表(HTML) 70 Page - ATMEL Corporation |
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70 / 107 page  70 T48C862-R4 [Preliminary] 4551C–4BMCU–01/04 Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. This can be used for clocking in a data telegram of less than 8 bits in length. Care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivat- ing the SSI (SIR = 1) and terminating the reception. After termination, the shift register contents will overwrite the receive buffer. Figure 66. Example of 8-bit Synchronous Transmit Operation Figure 67. Example of 8-bit Synchronous Receive Operation 76543 21 0 7 6 543 210 7 6 54 321 0 msb lsb tx data 1 tx data 2 tx data 3 msb lsb msb lsb Write STB (tx data 2) Write STB (tx data 3) Write STB (tx data 1) SC SD SIR SRDY Interrupt (IFN = 0) Interrupt (IFN = 1) ACT 43210 7 6 543 210 msb lsb rx data 1 rx data 2 rx data 3 msb lsb msb lsb Read SRB (rx data 2) Read SRB (rx data 3) Read SRB (rx data 1) SC SD SIR SRDY Interrupt (IFN = 0) Interrupt (IFN = 1) ACT 7 6 5 4 3210 76 5 7 6 5 4 |
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