T48C862-R4 datasheet(43/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Timer 1 Control Register 2

(T1C2)

Address: "7"hex - Subaddress: "9"hex

* Bit 3 -> MSB, Bit 0 -> LSB

Watchdog Control Register

(WDC)

Address: "7"hex - Subaddress: "A"hex

* Bit 3 -> MSB, Bit 0 -> LSB

Both these bits control the time interval for the watchdog reset.

Table 15.

Watchdog Time Control Bits

Bit 3 *

Bit 2

Bit 1

Bit 0

–

T1BP

T1CS

T1IM

Reset value: x111b

T1BP

imer 1 SUBCL ByPassed

T1BP = 1, TIOUT = T1MUX

T1BP = 0, T1OUT = SUBCL

T1CS

imer 1 input Clock Select

T1CS = 1, CL1 = SUBCL (see Figure 34 on page 41)

T1CS = 0, CL1 = SYSCL (see Figure 34 on page 41)

T1IM

imer 1 Interrupt Mask

T1IM = 1, disables Timer 1 interrupt

T1IM = 0, enables Timer 1 interrupt

Bit 3 *

Bit 2

Bit 1

Bit 0

WDL

WDR

WDT1

WDT0

Reset value: 1111b

WDL

atchDog Lock mode

WDL = 1, the watchdog can be enabled and disabled by using the WDR bit

WDL = 0, the watchdog is enabled and locked. In this mode the WDR bit has no

effect. After the WDL bit is cleared, the watchdog is active until a

system reset or power-on reset occurs.

WDR

atchDog Run and stop mode

WDR = 1, the watchdog is stopped/disabled

WDR = 0, the watchdog is active/enabled

WDT1

atchDog Time 1

WDT0

atchDog Time 0

WDT1

WDT0

Divider

Delay Time to Reset with

SUBCL = 32 kHz

Delay Time to Reset with

SYSCL = 2/1 MHz

512

15.625 ms

0.256 ms/0.512 ms

2048

62.5 ms

1.024 ms/2.048 ms

16384

0.5 s

8.2 ms/16.4 ms

131072

4 s

65.5 ms/131 ms

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