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T48C862-R4 数据表(PDF) 65 Page - ATMEL Corporation |
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T48C862-R4 数据表(HTML) 65 Page - ATMEL Corporation |
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65 / 107 page  65 T48C862-R4 [Preliminary] 4551C–4BMCU–01/04 Timer 3 Compare-Mode Register 1 (T3CM1) Address: "B"hex - Subaddress: "2"hex T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1 Timer 3 Compare Mode Register 2 (T3CM2) Address: "B"hex - Subaddress: "3"hex T3CM2 contains the mask bits for the match event of Counter 3 compare register 2 The compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program output signal. The single-action mask can also be used in this mode. It starts operating after the timer started with T3R. Bit 3Bit 2Bit 1Bit 0 T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 Reset value: 0000b T3SM1 T imer 3 Single action Mask bit 1 T3SM1 = 0, disables single-action compare mode T3SM1 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO1) is used until the next compare match. T3TM1 T imer 3 compare Toggle action Mask bit 1 T3TM1 = 0, disables compare toggle T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO1) toggles the output flip-flop (TOG3). T3RM1 T imer 3 Reset Mask bit 1 T3RM1 = 0, disables counter reset T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO1) resets the Counter 3. T3IM1 T imer 3 Interrupt Mask bit 1 T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register. T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register. Bit 3Bit 2Bit 1Bit 0 T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 Reset value: 0000b T3SM2 T imer 3 Single action Mask bit 2 T3SM2 = 0, disables single-action compare mode T3SM2 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO2) is used until the next compare match. T3TM2 T imer 3 compare Toggle action Mask bit 2 T3TM2 = 0, disables compare toggle T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO2) toggles the output flip-flop (TOG3). T3RM2 T imer 3 Reset Mask bit 2 T3RM2 = 0, disables counter reset T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO2) resets the Counter 3. T3IM2 T imer 3 Interrupt Mask bit 2 T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register. T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register. |
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