EDB8164B4PR-1DITF-R datasheet(116/152 Pages) MICRON

116 / 152 page

Input Slew Rate

Table 75: Differential Input Slew Rate Definition

Description

Measured1

Defined by

From

Differential input slew rate for rising

edge (CK_t/CK_c and DQS_t/DQS_c)

VIL,diff,max

VIH,diff,min

[VIH,diff,min - VIL,diff,maxΔTRdiff

Differential input slew rate for falling

edge (CK_t/CK_c and DQS_t/DQS_c)

VIH,diff,min

VIL,diff,max

[VIH,diff,min - VIL,diff,maxΔTFdiff

Note:

1. The differential signals (CK_t/CK_c and DQS_t/DQS_c) must be linear between these

thresholds.

Figure 75: Differential Input Slew Rate Definition for CK_t, CK_c, DQS_t, and DQS_c

IH,diff,min

IL,diff,max

Time

ΔTF

diff

ΔTR

diff

Output Characteristics and Operating Conditions

Table 76: Single-Ended AC and DC Output Levels

Symbol

Parameter

Value

Unit Notes

VOH(AC)

AC output HIGH measurement level (for output slew rate)

VREF + 0.12

VOL(AC)

AC output LOW measurement level (for output slew rate)

VREF - 0.12

VOH(DC)

DC output HIGH measurement level (for I-V curve linearity)

0.9 x VDDQ

VOL(DC)

DC output LOW measurement level (for I-V curve linearity)

0.1 x VDDQ

IOZ

Output leakage current (DQ, DM, DQS_t, DQS_c);

DQ, DQS_t, DQS_c are disabled; 0V

≤ V

OUT ≤ VDDQ

MIN

–5

μA

MAX

μA

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Output Characteristics and Operating Conditions

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

116

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDB8164B4PR-1DITF-R 数据表(PDF) 116 Page - Micron Technology

EDB8164B4PR-1DITF-R 数据表(HTML) 116 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载