XIO2000 datasheet(115/150 Pages) TI

115 / 150 page

PCI Express Extended Configuration Space

103

November 2005

SCPS097B

5.21 VC Resource Capability Register (VC0)

The VC resource capability register for VC0 provides information to software regarding the port and arbitration

schemes supported by the bridge. See Table 5−17 for a complete description of the register contents.

PCI Express extended register offset:

160h

Read-only

Default value:

0000 0001h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5−17. VC Resource Capability Register (VC0) Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:24

PORT_ARB_TBL_OFFSET

Port arbitration table offset. This read-only field returns the value 00h to indicate that

no port arbitration table is required for this VC.

RSVD

Reserved. Returns 0b when read.

22:16

MAX_TIME_SLOTS

Maximum time slots. This read-only field returns the value 000 0000b because there is

no support for time-based, WRR arbitration on this VC.

REJECT_SNOOP

Reject snoop transactions. This bit only has meaningful context for root ports;

therefore, returns 0b when read.

ADV_SWITCHING

Advanced packet switching. This read-only bit returns 0b to indicate that the use of this

VC is not limited to AS traffic.

13:8

RSVD

Reserved. Returns 00 0000b when read.

7:0

PORT_ARB_CAP

Port arbitration capability. This 8-bit encoded field indicates support for the various

schemes that are supported for port (secondary PCI device) arbitration. The field is

encoded as follows:

Bit 0 = Hardware fixed arbitration (round-robin)

Bit 1 = WRR with 32 phases

Bit 2 = WRR with 64 phases

Bit 3 = WRR with 128 phases

Bit 4 = Time-based WRR with 128 phases

Bit 5 = WRR with 256 phases

Bits 6 and 7 = Reserved

The returned value of 01h indicates that only hardware-fixed, round-robin arbitration is

support for this VC.

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