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XIO2000 数据表(PDF) 118 Page - Texas Instruments |
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XIO2000 数据表(HTML) 118 Page - Texas Instruments |
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118 / 150 page  PCI Express Extended Configuration Space 106 November 2005 SCPS097B 5.25 VC Resource Control Register (VC1) The VC resource control register for VC1 allows software to control the second VC and associated port and arbitration schemes supported by the bridge. See Table 5−21 for a complete description of the register contents. PCI Express extended register offset: 170h Register type: Read-only, Read/Write Default value: 0100 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5−21. VC Resource Control Register (VC1) Description BIT FIELD NAME ACCESS DESCRIPTION 31 VC_EN RW VC enable. This bit is used by software to enable this VC resource. Writing a 1b to this bit causes the bridge to begin VC negotiation and set bit 1 (VC_PENDING) in the VC resource status register for this VC (offset 176h, see Section 5.26). The default value for this bit is 0b. 30:27 RSVD R Reserved. Returns 0h when read. 26:24 VC_ID RW Virtual channel ID. This field allows software to assign a VC ID to this VC resource. Valid values range from 001b to 111b, because the value 000b is hardware-fixed to VC0 within the device. The default value for this field is 001b. 23:20 RSVD R Reserved. Returns 0h when read. 19:17 PORT_ARB _SELECT RW Port arbitration select. This read/write field allows software to define the mechanism used for port arbitration by the bridge on this VC. The value written to this field indicates the bit position within bits 7:0 (PORT_ARB_CAP) in the VC resource capability register for this VC (offset 16Ch, see Section 5.24) that corresponds to the selected arbitration scheme. Values that may be written to this field include: 000 = Hardware-fixed round-robin (default) 100 = Time-based WRR with 128 phases All other values are reserved for arbitrations schemes that are not supported by the bridge. 16 LOAD_PORT _TABLE RW Load port arbitration table. When software writes a 1b to this bit, the bridge applies the values written in the port arbitration table for this VC within the extended configuration space to the actual port arbitration tables used by the device for arbitration on this VC. This bit always returns 0b when read. 15:8 RSVD R Reserved. Returns 00h when read. 7:0 TC_VC_MAP RW TC/VC map. This field indicates all of the traffic classes that are mapped to this VC. A 1b in any bit position indicates that the corresponding traffic class is enabled for this VC. A 0b indicates that the corresponding traffic class is mapped to a different VC. The following table is used: Bit 0 = Traffic class 0 (This bit is read only and returns a value of 0b) Bit 1 = Traffic class 1 Bit 2 = Traffic class 2 Bit 3 = Traffic class 3 Bit 4 = Traffic class 4 Bit 5 = Traffic class 5 Bit 6 = Traffic class 6 Bit 7 = Traffic class 7 The default value of 00h indicates that none of the eight traffic classes are initially mapped to this VC. |
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