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XIO2000 数据表(PDF) 117 Page - Texas Instruments |
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XIO2000 数据表(HTML) 117 Page - Texas Instruments |
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117 / 150 page  PCI Express Extended Configuration Space 105 November 2005 SCPS097B 5.23 VC Resource Status Register (VC0) The VC resource status register allows software to monitor the status of the port arbitration table for this VC. See Table 5−19 for a complete description of the register contents. PCI Express extended register offset: 16Ah Register type: Read-only Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5−19. VC Resource Status Register (VC0) Description BIT FIELD NAME ACCESS DESCRIPTION 15:2 RSVD R Reserved. Returns 00 0000 0000 0000b when read. 1 VC_PENDING RU VC negotiation pending. This bit is asserted when VC negotiation is in progress following a request by software to enable or disable the VC or at startup for VC0. 0 PORT_TABLE_STATUS RU Port arbitration table status. This bit is automatically set by hardware when any modification is made to the port arbitration table entries for this VC within the extended configuration space. This bit is cleared by hardware after software has requested a port arbitration table refresh and the refresh has been completed. 5.24 VC Resource Capability Register (VC1) The VC resource capability register for VC1 provides information to software regarding the port and arbitration schemes supported by the bridge. See Table 5−20 for a complete description of the register contents. PCI Express extended register offset: 16Ch Register type: Read-only Default value: 077F 0011h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Table 5−20. VC Resource Capability Register (VC1) Description BIT FIELD NAME ACCESS DESCRIPTION 31:24 PORT_ARB_ TBL_OFFSET R Port arbitration table offset. This read-only field returns the value 07h to indicate that the port arbitration table for this VC begins 112 bytes from the top of the VC capability structure. 23 RSVD R Reserved. Returns 0b when read. 22:16 MAX_TIME_ SLOTS R Maximum time slots. The read-only field returns the value 111 1111b to indicate that all 128 slots are supported for time-based WRR. 15 REJECT_ SNOOP R Reject snoop transactions. This bit only has meaningful context for root ports; therefore, returns 0b when read. 14 ADV_ SWITCHING R Advanced packet switching. This read-only bit returns the value 0b to indicate that the use of this VC is not limited to AS traffic. 13:8 RSVD R Reserved. Return 00 0000b when read. 7:0 PORT_ ARB_CAP R Port arbitration capability. This 8-bit encoded field indicates support for the various schemes that are supported for port (secondary PCI device) arbitration. The field is encoded as follows: Bit 0 = Hardware fixed arbitration (round-robin) Bit 1 = WRR with 32 phases Bit 2 = WRR with 64 phases Bit 3 = WRR with 128 phases Bit 4 = Time-based WRR with 128 phases Bit 5 = WRR with 256 phases Bits 6 and 7 = Reserved The returned value of 11h indicates that hardware-fixed round-robin and time-based WRR with 128 phases are both supported. |
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