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TDA4VEN...Q1 数据表(PDF) 43 Page - Texas Instruments

部件名 TDA4VEN...Q1
功能描述  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4VEN...Q1 数据表(HTML) 43 Page - Texas Instruments

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Table 5-1. Pin Attributes (AMW Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL STATE
DURING
RESET
(RX/TX/PULL) [7]
BALL STATE
AFTER
RESET
(RX/TX/PULL) [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
AA24
VOUT0_DATA8
PADCONFIG
PADCONFIG54
0x000F40D8
VOUT0_DATA8
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
GPMC0_A8
1
OZ
RGMII2_TX_CTL
2
O
RMII2_TX_EN
3
O
UART6_RXD
4
I
1
MCASP3_AXR4
6
IO
0
GPIO0_53
7
IO
pad
AA27
VOUT0_DATA9
PADCONFIG
PADCONFIG55
0x000F40DC
VOUT0_DATA9
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
GPMC0_A9
1
OZ
RGMII2_TXC
2
O
RMII2_CRS_DV
3
I
0
UART6_TXD
4
O
MCASP3_AXR5
6
IO
0
GPIO0_54
7
IO
pad
AA25
VOUT0_DATA10
PADCONFIG
PADCONFIG56
0x000F40E0
VOUT0_DATA10
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
GPMC0_A10
1
OZ
RGMII2_TD0
2
O
RMII2_TXD0
3
O
UART6_RTSn
4
O
MCASP4_AXR6
6
IO
0
GPIO0_55
7
IO
pad
MCASP4_ACLKR
8
IO
0
AB25
VOUT0_DATA11
PADCONFIG
PADCONFIG57
0x000F40E4
VOUT0_DATA11
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
GPMC0_A11
1
OZ
RGMII2_TD1
2
O
RMII2_TXD1
3
O
UART6_CTSn
4
I
1
MCASP4_AXR7
6
IO
0
GPIO0_56
7
IO
pad
MCASP4_AFSR
8
IO
0
AA23
VOUT0_DATA12
PADCONFIG
PADCONFIG58
0x000F40E8
VOUT0_DATA12
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
GPMC0_A12
1
OZ
RGMII2_TD2
2
O
UART5_RTSn
4
O
MCASP4_AXR0
6
IO
0
GPIO0_57
7
IO
pad
www.ti.com
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1



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