TDA4VEN...Q1 datasheet(98/236 Pages) TI

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(6)

The VMON_1P8_SOC input is used to monitor supply voltage and shall be connected to the respective 1.8V supply source.

(7)

VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any dependency on

other power rails. This capability is required to support UHS-I SD Cards.

(8)

VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together.

(9)

VDD_CANUART shall be connected to an always-on power source when using Partial IO low power mode.

When VDD_CANUART is connected to an always-on power source, the potential applied to VDD_CORE must never be greater than

the potential applied to VDD_CANUART + 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before

and ramp down after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for VDD_CORE.

(10) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK,

VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.

VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 can

be operated at 0.75V or 0.85V. When these supplies are operating at 0.75V, they shall be ramped up prior to VDDR_CORE as defined

by this waveform.

(11) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK,

VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.

VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 can

be operated at 0.75V or 0.85V. When these supplies are operating at 0.85V, they shall be powered from the same source as

VDDR_CORE and ramped during the 0.85V ramp period defined by this waveform.

(12) The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or

power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at

0.75V. VDD_CORE does not have any ramp requirements beyond the one defined for VDDR_CORE.

VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is

operating at 0.85V.

(13) VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/down sequences and

during normal device operation. This supply shall only be sourced while programming eFuse.

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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TDA4VEN...Q1 数据表(PDF) 98 Page - Texas Instruments