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TDA4VEN...Q1 数据表(PDF) 60 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 60 Page - Texas Instruments |
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60 / 236 page  Table 5-28. MCU_GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] MCU_GPIO0_8 (1) IO General Purpose Input/Output C5 MCU_GPIO0_9 IO General Purpose Input/Output B3 MCU_GPIO0_10 IO General Purpose Input/Output C8 MCU_GPIO0_11 (1) IO General Purpose Input/Output C4 MCU_GPIO0_12 (1) IO General Purpose Input/Output C3 MCU_GPIO0_13 IO General Purpose Input/Output B2 MCU_GPIO0_14 IO General Purpose Input/Output D8 MCU_GPIO0_15 (1) IO General Purpose Input/Output C1 MCU_GPIO0_16 (1) IO General Purpose Input/Output B1 MCU_GPIO0_17 IOD General Purpose Input/Output B13 MCU_GPIO0_18 IOD General Purpose Input/Output E11 MCU_GPIO0_19 IOD General Purpose Input/Output B9 MCU_GPIO0_20 IOD General Purpose Input/Output D11 MCU_GPIO0_21 IO General Purpose Input/Output E13 MCU_GPIO0_22 IO General Purpose Input/Output A8 MCU_GPIO0_23 IO General Purpose Input/Output F12 (1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. 5.3.12 GPMC 5.3.12.1 MAIN Domain Table 5-29. GPMC0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] GPMC0_ADVn_ALE O GPMC Address Valid (active low) or Address Latch Enable N21 GPMC0_CLK O GPMC clock T23 GPMC0_DIR O GPMC Data Bus Signal Direction Control N25 GPMC0_FCLK_MUX O GPMC functional clock output T23 GPMC0_OEn_REn O GPMC Output Enable (active low) or Read Enable (active low) N22 GPMC0_WEn O GPMC Write Enable (active low) N23 GPMC0_WPn O GPMC Flash Write Protect (active low) N24 GPMC0_A0 OZ GPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memories W27 GPMC0_A1 OZ GPMC address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed mode W25 GPMC0_A2 OZ GPMC address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed mode W24 GPMC0_A3 OZ GPMC address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed mode W23 GPMC0_A4 OZ GPMC address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed mode W22 GPMC0_A5 OZ GPMC address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed mode W21 GPMC0_A6 OZ GPMC address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed mode Y26 GPMC0_A7 OZ GPMC address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed mode Y27 TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 60 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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