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TDA4VEN...Q1 数据表(PDF) 19 Page - Texas Instruments

部件名 TDA4VEN...Q1
功能描述  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4VEN...Q1 数据表(HTML) 19 Page - Texas Instruments

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Table 5-1. Pin Attributes (AMW Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL STATE
DURING
RESET
(RX/TX/PULL) [7]
BALL STATE
AFTER
RESET
(RX/TX/PULL) [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
U27
GPMC0_AD8
PADCONFIG
PADCONFIG23
0x000F405C
GPMC0_AD8
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA16
1
O
UART2_RXD
2
I
1
MCASP2_AXR0
3
IO
0
GPIO0_23
7
IO
pad
BOOTMODE08
Bootstrap
I
U26
GPMC0_AD9
PADCONFIG
PADCONFIG24
0x000F4060
GPMC0_AD9
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA17
1
O
UART2_TXD
2
O
MCASP2_AXR1
3
IO
0
GPIO0_24
7
IO
pad
BOOTMODE09
Bootstrap
I
V27
GPMC0_AD10
PADCONFIG
PADCONFIG25
0x000F4064
GPMC0_AD10
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA18
1
O
UART3_RXD
2
I
1
MCASP2_AXR2
3
IO
0
GPIO0_25
7
IO
pad
OBSCLK0
8
O
BOOTMODE10
Bootstrap
I
V25
GPMC0_AD11
PADCONFIG
PADCONFIG26
0x000F4068
GPMC0_AD11
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA19
1
O
UART3_TXD
2
O
MCASP2_AXR3
3
IO
0
TRC_DATA23
6
O
GPIO0_26
7
IO
pad
BOOTMODE11
Bootstrap
I
V26
GPMC0_AD12
PADCONFIG
PADCONFIG27
0x000F406C
GPMC0_AD12
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA20
1
O
UART4_RXD
2
I
1
MCASP2_AFSX
3
IO
0
TRC_DATA22
6
O
GPIO0_27
7
IO
pad
BOOTMODE12
Bootstrap
I
www.ti.com
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1



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