TDA4VEN...Q1 datasheet(78/236 Pages) TI

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Table 5-81. USB0 Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE

[2]

DESCRIPTION [3]

AMW PIN [4]

USB0_DRVVBUS

USB VBUS control output (active high)

E25

USB0_RCALIB (1)

Pin to connect to calibration resistor

AA8

USB0_VBUS (2)

USB Level-shifted VBUS Input

(1)

An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is

7.2mW. No external voltage should be applied to this pin.

(2)

An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.2.3, USB

VBUS Design Guidelines.

Table 5-82. USB1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE

[2]

DESCRIPTION [3]

AMW PIN [4]

USB1_DM

USB 2.0 Differential Data (negative)

E17

USB1_DP

USB 2.0 Differential Data (positive)

D17

USB1_DRVVBUS

USB VBUS control output (active high)

B27

USB1_RCALIB (1)

Pin to connect to calibration resistor

E18

USB1_VBUS (2)

USB Level-shifted VBUS Input

F18

(1)

An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is

7.2mW. No external voltage should be applied to this pin.

(2)

An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.2.3, USB

VBUS Design Guidelines.

5.4 Pin Connectivity Requirements

This section describes connectivity requirements for package balls that have specific connectivity requirements

and unused package balls.

Note

All power pins must be supplied with the voltages specified in Recommended Operating Conditions,

unless otherwise specified.

Note

For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be

connected to these device ball numbers.

Table 5-83. Connectivity Requirements

AMW

BALL

NUMBER

BALL NAME

CONNECTION REQUIREMENTS

B10

TRSTn

Each of these balls must be connected to VSS through separate external pull

resistors to ensure these balls are held to a valid logic-low level if a PCB signal

trace is connected and not actively driven by an attached device. The internal

pull-down can be used to hold a valid logic-low level if no PCB signal trace is

connected to the ball.

A11

E12

F11

TCK

TDI

TMS

Each of these balls must be connected to the corresponding power supply(1)

through separate external pull resistors to ensure the inputs associated with

these balls are held to a valid logic-high level if a PCB signal trace is connected

and not actively driven by an attached device. The internal pull-up can be used

to hold a valid logic-high level if no PCB signal trace is connected to the ball.

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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