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TDA4VEN...Q1 数据表(PDF) 72 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 72 Page - Texas Instruments |
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72 / 236 page  Table 5-58. Reserved Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] RSVD8 N/A Reserved, must be left unconnected AA15 RSVD9 N/A Reserved, must be left unconnected AA14 RSVD10 N/A Reserved, must be left unconnected L5 RSVD11 N/A Reserved, must be left unconnected M6 RSVD12 N/A Reserved, must be left unconnected AB16 RSVD13 N/A Reserved, must be left unconnected AB18 RSVD14 N/A Reserved, must be left unconnected C6 RSVD15 N/A Reserved, must be left unconnected F8 RSVD16 N/A Reserved, must be left unconnected B6 RSVD17 N/A Reserved, must be left unconnected C17 RSVD18 N/A Reserved, must be left unconnected D16 RSVD19 N/A Reserved, must be left unconnected D14 RSVD20 N/A Reserved, must be left unconnected D13 RSVD21 N/A Reserved, must be left unconnected M2 5.3.23 SERDES 5.3.23.1 MAIN Domain Table 5-59. PCIE0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] PCIE0_CLKREQn IOD PCIE Clock Request Signal F25 Table 5-60. SERDES0 Signal Descriptions SIGNAL NAME [1] ((2)) PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] SERDES0_REXT (1) A SERDES PHY External Calibration Resistor E15 SERDES0_REFCLK0N IO SERDES PHY Reference Clock Input/Output (negative) A17 SERDES0_REFCLK0P IO SERDES PHY Reference Clock Input/Output (positive) A16 SERDES0_RX0_N I SERDES PHY Differential Receive Data (negative) A20 SERDES0_RX0_P I SERDES PHY Differential Receive Data (positive) A19 SERDES0_TX0_N O SERDES PHY Differential Transmit Data (negative) B19 SERDES0_TX0_P O SERDES PHY Differential Transmit Data (positive) B18 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) The functionality of these pins is controlled by SERDES0_LN0_CTRL. Table 5-61. SERDES1 Signal Descriptions SIGNAL NAME [1] ((2)) PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] SERDES1_REXT (1) A SERDES PHY External Calibration Resistor F14 SERDES1_REFCLK0N IO SERDES PHY Reference Clock Input/Output (negative) B15 SERDES1_REFCLK0P IO SERDES PHY Reference Clock Input/Output (positive) B16 SERDES1_RX0_N I SERDES PHY Differential Receive Data (negative) C14 SERDES1_RX0_P I SERDES PHY Differential Receive Data (positive) C15 SERDES1_TX0_N O SERDES PHY Differential Transmit Data (negative) A13 SERDES1_TX0_P O SERDES PHY Differential Transmit Data (positive) A14 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 72 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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